1. Field of the Invention
The present invention relates in general to on-screen display circuits, and more particularly to an on-screen display circuit for displaying characters or pictures successively like motion captions.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional on-screen display (referred to hereinafter as OSD) circuit. As shown in this drawing, the conventional OSD circuit comprises an oscillation control/synchronization circuit 1 for generating a vertical clock signal YCLK in response to a horizontal synchronous signal Hsync and a horizontal clock signal XCLK in response to a reference clock signal OSC. The vertical and horizontal clock signals YCLK and XCLK from the oscillation control/synchronization circuit 1 designate vertical and horizontal positions on a screen, respectively. Also, the oscillation control/synchronization circuit 1 inputs a vertical synchronous signal Vsync and outputs the inputted vertical synchronous signal Vsync.
The conventional OSD circuit also comprises a vertical position detector 2 being reset in response to the vertical synchronous signal Vsync from the oscillation control/synchronization circuit 1 to count the vertical clock signal YCLK from the oscillation control/synchronization circuit 1 and generate a vertical position signal VDS in accordance with the counted result. The vertical position signal VDS from the vertical position detector 2 designates a vertical position of a character to be displayed on the screen.
Also, the conventional OSD circuit comprises a horizontal position detector 3 being enabled in response to the vertical position signal VDS from the vertical position detector 2 to count the horizontal clock signal XCLK from the oscillation control/synchronization circuit 1 and generate a horizontal position signal HPS in accordance with the counted result. The horizontal position signal HPS from the horizontal position detector 3 designates a horizontal position of the character to be displayed on the screen.
Further, the conventional OSD circuit comprises a vertical dot counter 4 being enabled in response to the vertical position signal VDS from the vertical position detector 2 to frequency-divide the vertical clock signal YCLK from the oscillation control/synchronization circuit 1 by a vertical size of the character to be displayed on the screen, count the frequency-divided vertical clock signal YCLK and generate a row address ADDR in accordance with the counted result, a horizontal dot clock generator 5 being enabled in response to the horizontal position signal HPS from the horizontal position detector 3 to frequency-divide the horizontal clock signal XCLK from the oscillation control/synchronization circuit 1 by a horizontal size of the character to be displayed on the screen and output the frequency-divided horizontal clock signal XCLK as a horizontal dot clock signal HDCLK, and a random access memory (referred to hereinafter as RAM) address generator 6 being reset in response to the vertical clock signal YCLK from the oscillation control/synchronization circuit 1 to frequency-divide the horizontal dot clock signal HDCLK from the horizontal dot clock generator 5 by the number of horizontal dots of one character, count the frequency-divided horizontal dot clock signal HDCLK and generate a read address RADD in accordance with the counted result.
Further, the conventional OSD circuit comprises an on-screen RAM 7 for outputting a character address ADDC and corresponding color data CD in its location corresponding to the read address RADD from the RAM address generator 6, a column selector 8 for determining a column address of the character to be displayed on the screen, in response to the character address ADDC from the on-screen RAM 7, a row decoder 9 for decoding the row address ADDR from the vertical dot counter 4, a font ROM 10 for outputting character data in its location corresponding to column and row addresses from the column selector 8 and the row decoder 9, a shift register 11 for converting the character data from the font ROM 10 into serial font data SFD synchronously with the horizontal dot clock signal HDCLK from the horizontal dot clock generator 5, and a display mode/output controller 12 for generating red (R), green (G) and blue (B) color signals and a switching signal Y according to a designated display mode in response to the serial font data SFD from the shift register 11 and the color data CD from the on-screen RAM 7.
The operation of the conventional OSD circuit with the above-mentioned construction will hereinafter be described.
First, in FIG. 1, the horizontal and vertical synchronous signals Hsync and Vsync are separated from a broadcasting signal and then applied to the oscillation control/synchronization circuit 1, which also inputs the reference clock signal OSC. The oscillation control/synchronization circuit 1 generates the vertical clock signal YCLK in response to the horizontal synchronous signal Hsync to designate the vertical position on the screen. Also, the oscillation control/synchronization circuit 1 generates the horizontal clock signal XCLK in response to the reference clock signal OSC to designate the horizontal position on the screen. Further, the oscillation control/synchronization circuit 1 inputs the vertical synchronous signal Vsync and outputs the inputted vertical synchronous signal Vsync to the vertical position detector 2. The horizontal clock signal XCLK from the oscillation control/synchronization circuit 1 is applied to the horizontal position detector 3 and the horizontal dot clock generator 5. The vertical clock signal YCLK from the oscillation control/synchronization circuit 1 is applied to the vertical position detector 2, the horizontal position detector 3, the vertical dot counter 4 and the RAM address generator 6. The vertical position detector 2 is reset in response to the vertical synchronous signal Vsync from the oscillation control/synchronization circuit 1 to count the vertical clock signal YCLK from the oscillation control/synchronization circuit 1. As a result of the counting, the vertical position detector 2 generates the vertical position signal VDS to designate the vertical position of the character to be displayed on the screen. The vertical position signal VDS from the vertical position detector 2 is applied to the horizontal position detector 3 and the vertical dot counter 4.
When the vertical position signal VDS from the vertical position detector 2 is made active, the vertical dot counter 4 is enabled. As being enabled, the vertical dot counter 4 frequency-divides the vertical clock signal YCLK from the oscillation control/synchronization circuit 1 by the vertical size of the character to be displayed on the screen and counts the frequency-divided vertical clock signal YCLK. As a result of the counting, the vertical dot counter 4 generate the row address ADDR of the font ROM 10 in accordance with the counted result. The row address ADDR from the vertical dot counter 4 is applied to the row decoder 9.
Referring to FIG. 2, there is shown a detailed block diagram of the horizontal position detector 3 in FIG. 1. As shown in this drawing, the horizontal position detector 3 includes a horizontal position register 3A for storing a horizontal position value of an OSD region, and a down counter 3B for down-counting the horizontal position value of the OSD region from the horizontal position register 3A in response to the horizontal clock signal XCLK from the oscillation control/synchronization circuit 1. As the vertical clock signal YCLK from the oscillation control/synchronization circuit 1 is applied, the horizontal position value of the OSD region stored in the horizontal position register 3A is loaded into the down counter 3B. The down counter 3B down-counts the loaded horizontal position value of the OSD region from the horizontal position register 3A in response to the horizontal clock signal XCLK from the oscillation control/synchronization circuit 1. Then, the down counter 3B generates the horizontal position signal HPS at the moment that its count reaches "0". In result, the horizontal position signal HPS from the down counter 3B indicates a start point of a horizontal display position of the OSD region. Heret the down counter 3B is enabled when the vertical position signal VDS from the vertical position detector 2 is made active. Then, the horizontal position signal HPS from the down counter 3B is applied to the horizontal dot clock generator 5 in FIG. 1.
Referring again to FIG. 1, the horizontal dot clock generator 5 is enabled when the horizontal position signal HPS from the horizontal position detector 3 is made active. As being enabled, the horizontal dot clock generator 5 frequency-divides the horizontal clock signal XCLK from the oscillation control/synchronization circuit 1 by the horizontal size of the character to be displayed on the screen and outputs the frequency-divided horizontal clock signal XCLK as the horizontal dot clock signal HDCLK to the RAM address generator 6 and the shift register 11.
Referring to FIG. 3, there is shown a detailed block diagram of the RAM address generator 6 in FIG. 1. As shown in this drawing, the RAM address generator 6 includes a frequency divider 6A for frequency-dividing the horizontal dot clock signal HDCLK from the horizontal dot clock generator 5 by the number of the horizontal dots of one character and outputting the frequency-divided horizontal dot clock signal HDCLK as a character clock signal CHCLK at an interval of character, and an up-counter 6B for up-counting the character clock signal CHCLK from the, frequency divider 6A and generating the read address RADD of the on-screen RAM in accordance with the counted result. Here, the up-counter 6B is reset in response to the vertical clock signal YCLK from the oscillation control/synchronization circuit 1. The read address RADD from the up-counter 6B is applied to the on-screen RAM 7.
Referring again to FIG. 1, the on-screen RAM 7 stores the character addresses ADDC and the corresponding color data CD. Upon receiving the read address RADD from the RAM address generator 6, the on-screen RAM 7 outputs the character address ADDC and the corresponding color data CD in its location corresponding to the received read address RADD. The character address ADDC from the on-screen RAM 7 is applied to the column selector 8 and the color data CD therefrom is applied to the display mode/output controller 12. The column selector 8 designates the column address of the font ROM 10 in response to the character address ADDC from the on-screen RAM 7. The row decoder 9 decodes the row address ADDR from the vertical dot counter 4 and outputs the decoded signal to the font ROM 10 to designate the row address thereof.
The font ROM stores the character font data in the form of code. Upon receiving the column and row addresses from the column selector 8 and the row decoder 9, the font ROM 10 outputs the character data in its location corresponding to the received column and row addresses. The character data from the font ROM 10 is loaded into the shift register 11. The shift register 11 converts the loaded character data from the font ROM 10 into the serial font data SFD using the horizontal dot clock signal HDCLK from the horizontal dot clock generator 5 as a shift clock. The serial font data SFD from the shift register 11 is applied to the display mode/output controller 12. Using the serial font data SFD from the shift register 11 and the color data CD from the on-screen RAM 7, the display mode/output controller 12 generates the R, G and B color signals and the switching signal Y according to the designated display mode. The switching signal Y from the display mode/output controller 12 acts to block a broadcasting signal corresponding to the OSD region so that it cannot be displayed on the screen.
However, in the above-mentioned conventional OSD circuit, a large amount of information is displayed as a plurality of lines on the screen in a multi-line manner. In this case, an original picture is not seen well on the screen because the OSD signal possesses a large portion of the screen.